课程

教学相长

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第一章 概述
第二章 Nios II处理器体系结构
第三章 Avalon接口规范
第四章 SOPC软硬件开发平台
第五章 Nios II处理器常用外设
第六章 μC/OS II操作系统移植
第七章 Nios II系统深入设计
第八章 调试技术

Nios II介绍

from: https://www.altera.com/products/processors/overview.html

Overview

Nios II Processor: The World's Most Versatile Embedded Processor

Altera's Nios® II processor, the world's most versatile processor, according to Gartner Research, is the most widely used soft processor in the FPGA industry. The Nios II processor delivers unprecedented flexibility for your cost-sensitive, real-time, safety-critical (DO-254), ASIC-optimized, and applications processing needs. The Nios II processor supports all Altera® SoC and FPGA families.

What makes the Nios II processor the world's most versatile processor?

Application

Nios II
Processor Core

Vendor

Description

Altera

Power and cost sensitive

Nios II economy core

Altera

With as low as 600 logic elements, the Nios II economy processor core is ideal for microcontroller applications. The Nios II economy processor core, software tools, and device drivers are offered free of charge.

Real time

Nios II standard and fast core

Altera

Absolutely deterministic, jitter free real-time performance with unique hardware real-time features

·         Vector Interrupt Controller

·         Tightly Coupled Memory

·         Custom instructions (ability to use FPGA hardware to accelerate a function)

·         Supported by industry-leading real-time operating systems (RTOS)

·         Nios II processor is the ideal real-time processor to use with DSP Builder-based hardware accelerators to provide deterministic, high performance real-time results

Applications processing

Nios II fast core

Altera

With a simple configuration option, the Nios II fast processor core can use a memory management unit (MMU) to run embedded Linux. Both open source and commercially supported versions of Linux for Nios II processors are available.

Altera Embedded Alliance

Safety critical

Nios II SC core

HCell

Certify your design for DO-254 compliance by using the Nios II Safety Critical procesor core along with the DO-254 compliance design services offered by HCell.

Get Started Now

 
Start your design today with the Nios II processor by purchasing one of the many low-cost evaluation or development kits available for the Nios II processor.

To ship designs featuring the Nios II processor, you will need to purchase a license for the Nios II processor.

Table 1. Processor Performance (MIPS* at fMAX) by Device

Processor Category

Cost- and Power-Sensitive Processors

Real-Time Processors

Applications Processor

Devices

ARM
Cortex-M1

V1 ColdFire

Nios II
Economy

Nios II
Standard

Nios II
Fast

ARM
Cortex-A9

Cyclone III
(MIPS
(1) at MHz)

80 at
145

84 at
90

30 at
215

90 at
145

195 at
175

-

Cyclone III LS
(MIPS
(1) at MHz)

-

65 at
70

20 at
150

70 at
110

160 at
140

-

Cyclone IV GX
(MIPS
(1) at MHz)

-

70 at
75

30 at
175

70 at
110

190 at
165

-

Arria II GX
(MIPS
(1) at MHz)

-

84 at
90

45 at
300

115 at
180

270 at
240

-

Stratix III
(MIPS
(1) at MHz)

150 at
230

104 at
112

48 at
340

140 at
230

340 at
290

-

Stratix IV
(MIPS
(1) at MHz)

-

135 at
145

50 at
340

155 at
240

340 at
290

-

Stratix V
(MIPS
(1) at MHz)

-

135 at
145

50 at
330

170 at
270

320 at
280

-

Notes for Table 1 and Table 2:

1.  Dhrystones 2.1 benchmark

2.  Per processor

Table 2. Processor Selector by Operating System Support

Processor Category

Low-Cost Processors

Real Time

Applications Processor

Features

Supplier

ARM
Cortex-M1

V1 ColdFire

Nios II

ARM
Cortex-A9

eCos

eCosCentric

-

-

Yes

-

eCos (Zylin)

Zylin

-

-

Yes

-

embOS

Segger

-

Yes

Yes

-

Erika Enterprice

Evidence

-

-

Yes

-

Euros RTOS

Euros

-

-

Yes

-

Linux

Wind River

-

-

Yes

-

Linux

Timesys

-

-

Yes

-

Linux

SLS

-

-

Yes

-

Linux

Open Source

-

-

Yes

Yes

MicroC/OS-II

Micrium

-

-

Yes

-

oSCAN

Vector

-

-

Yes

-

ThreadX

Express Logic

-

Yes

Yes

-

uCLinux

Open Source

 

-

-

Yes

-

VxWorks

Wind River

-

-

No

Yes

 

Features

Nios II Processor Feature Set and Performance

Nios II processor comprises family of three configurable 32 bit Harvard architecture cores:

Summary of Perfomance

  • Download the latest Nios II processor performance benchmarks data sheet

Summary of Features Supported

  • MMU
  • Memory protection unit (MPU)
  • External Vector Interrupt Controller with up to 32 interrupts per controller
  • Advanced exception support
  • Separate instruction and data caches (configurable from 512 bytes to 64 KB)
  • Access to up to 2 GB of external address space
  • Optional tightly-coupled memory for instructions and data
  • Up to six-stage pipeline to achieve maximum MIPS* (*Dhrystones 2.1 benchmark) per MHz
  • Single-cycle hardware multiply and barrel shifter
  • Hardware divide option
  • Dynamic branch prediction
  • Up to 256 custom instructions and unlimited hardware accelerators
  • Configurable JTAG debug module
  • Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace

Industries Most Advanced System Integration and Debug Tools

  • Quartus II software includes Qsys, the industry most advanced system integration tool for processor system design. With Qsys, designers integrate processors, peripherals, memory controller, communication controllers, and custom intellectual proeprty (IP) cores in a graphical user interface and the tool automatically generates high performance system interconnect logic.
  • Quartus II software system debug capabilities provide advanced debug capabilities at every level of the design:
    • Transceiver and Memory Tool Kit for protocol and memory debugging
    • SignalTapTM II logic analyzer for signal and logic level transactions
    • Signal Probe for IO level transactions
    • System Console for register level transactions

Free Embedded Peripheral IP Cores

  • Rich portfolio of Qsys-ready embedded peripheral intellectual property (IP) cores that are provided at no cost
    • DMA Controller
    • Scatter Gather DMA Controller
    • SDR SDRAM Controller
    • CFI Flash Controller
    • EPCS Serial Flash Controller
    • JTAG UART Controller
    • UART Controller
    • SPI Controller
    • PIO Controller
    • Mutex Core
    • Mailbox Core
    • Timer Core
    • Vector Interrupt Controller Core
    • Performance Counter
    • Phase-locked loop (PLL)
    • Avalon® Interconnect Components

Free Embedded Software Tools, Software, and Middleware

Everything you need to develop robust software applications is provided for you in the Nios II EDS. You'll feel right at home with the Eclipse-based Nios II Software Build Tools for Eclipse and a full range of software and operating system support provided by Altera and its partners.

  • The Nios II EDS includes:
    • Nios II Software Build Tools for Eclipse, a fully integrated graphcial development environment
    • GNU tools (GCC compiler, GDB debugger)
    • Software examples and templates, device drivers and bare metal HAL
    • Free Nichestack TCP/IP Network Stack, Nios II Edition, commercial grade network stack
    • Evalution version of Micrium's popular MicroC/OS-II RTOS

See what's new in the latest release of Nios II EDS.

Ecosystem

Embedded Operating Systems for the Nios II Processor

Operating System

Associated Processor

Supplier

eCos

Nios® II

eCosCentric

eCos

Nios II

Zylin

embOS

Nios II

Segger

Euros RTOS

Nios II

Euros

Linux

Nios II

Timesys

Linux

Nios II

Wind River

Linux

Nios II

SLS

Linux

Nios II

CodeSourcery

Linux

Nios II

Open Source Community

MicroC/OS-II (1)

Nios II

Micrium

osCAN (2)

Nios II

Vector

ThreadX

Nios II

Express Logic

µCLinux

Nios II

SLS

µCLinux

Nios II

Open Source Community

Notes:

1.  Evaluation included with the Nios II Embedded Design Suite, but licensed separately.

2.  OSEK/VDX compliant. OSEK/VDX is an open standard of the automotive industry.

Middleware & Graphics Libraries

Company Name

OS Supported

Network Stack

File System

Graphics Library

USB Stack

Miscellaneous

eCosCentric

eCos

Built in

Built in

-

-

-

Express Logic

ThreadX

NetX (1)

FileX (1)

PegX (1)

USBX (1)

-

InterNiche

Any

NicheStack TCP/IP Network Stack – Nios II Edition (2)

-

-

-

-

Mentor Graphics

Nucleus Plus

Nucleus Net

Nucleus File (1)

Nucleus GRAFIX (1)

Nucleus USB (1)

-

Micrium

MicroC/OS-II

MicroC/TCP-IP

MicroC/FS

MicroC/GUI

MicroC/USB

MicroC/CAN

Micro Digital

Any

-

-

-

-

GoFast floating-point library

Timesys

Linux

Built in

Built in

-

-

-

Wind River

Linux

Built in

Built in

-

-

-

SLS

µCLinux /Linux

Built in

Built in

-

USB 2.0

-

Community supported(www.alterawiki.com)
(Nios Forum area of the Altera Forum)

µCLinux /Linux

Built in

Built in

-

-

-

Altera

Any

-

Read-only zip file system (3)

-

-

-

Notes:

1.  Contact company for availability.

2.  Included with the Nios II Embedded Design Suite, but licensed separately.

3.  Included with the Nios II Embedded Design Suite.

Software Development Tools

Company

Product

Description

Wind River

Workbench
for Nios II embedded processor

Software development tools for embedded Linux on the Nios II processor.

Mentor Embedded

Sourcery CodeBench

GNU toolchain support for embedded Linux on the Nios II processor.

Mentor Embedded

Sourcery CodeBench

GNU toolchain support for the dual-core ARM Cortex-A9 MPCore processor-based SoC Virtual Target.

Altium

Tasking VX-toolset

Optimizing C compiler, assembler, linker, and locator.

MIPS Technologies (formerly FS2)

System Navigator

The System Navigator probe for Nios II processors is designed to support the special features and integrated peripherals of the Nios II cores embedded in Altera FPGAs.

Open-source community

Linux toolchain

Linux toolchain from the open-source community.

Open-source community

µCLinux toolchain

µLinux toolchain from the open-source community.