RTL simulation

RTL是寄存器传输级（register transfer level）的缩写。

In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals.

Register-transfer-level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Design at the RTL level is typical practice in modern digital design.

RTL is used in the logic design phase of the integrated circuit design cycle.

An RTL description is usually converted to a gate-level description of the circuit by a logic synthesis tool. The synthesis results are then used by placement and routing tools to create a physical layout.

Logic simulation tools may use a design's RTL description to verify its correctness.

RTL仿真直接仿真代码，没有时序（timing）信息，支持VHDL和Verilog语言。

门级仿真（Gate Leve simulation）是编译后网表（netlist）的仿真，包含时序信息，所以其支持任意的电路描述形式，由于层级比RTL低，所以仿真所需时间也比RTL长。