网表 Netlist
百度百科
由于逻辑门阵列有着连线表一样的排列外观，因此称之为“网表”。
网表通常传递了电路连接方面的信息，例如模块的实例、线网以及相关属性。
如果需要包含更多的硬件信息，通常会使用硬件描述语言，例如Verilog、VHDL或其他的专用语言来进行描述、验证和仿真。高抽象层次（如寄存器传输级）的硬件描述可以通过逻辑综合转换为低抽象层次（逻辑门级）的电路连线网表，这一步骤目前可以使用自动化工具完成，这也大大降低了设计人员处理超大规模集成电路的繁琐程度。硬件厂商利用上述网表，可以制造具体的专用集成电路或其他电路。一些相对较小的电路也可以在现场可编程逻辑门阵列上实现。
根据不同的分类，网表可以是物理或逻辑的，也可以是基于实例或基于线网的，抑或是平面的或多层次的，等等。
wikipedia
Netlist
A single netlist is effectively a collection of several related lists. In its simplest form, a netlist consists of a list of the terminals ("pins") of the electronic components in a circuit and a list of the electrical conductors that interconnect the terminals. A net is a conductor that interconnects two or more component terminals.
The structure, complexity and representation of netlists can vary considerably, but the fundamental purpose of every netlist is to convey connectivity information. Netlists usually provide nothing more than instances, nets, and perhaps some attributes. If they express much more than this, they are usually considered to be a hardware description language such as Verilog or VHDL, or one of several languages specifically designed for input to simulators.
Netlists can be physical or logical, instance-based or net-based, and flat or hierarchical. The latter can be either folded or unfolded.