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第一章 概述
第二章 Nios II处理器体系结构
第三章 Avalon接口规范
第四章 SOPC软硬件开发平台
第五章 Nios II处理器常用外设
第六章 μC/OS II操作系统移植
第七章 Nios II系统深入设计
第八章 调试技术

Nios II processor architecute

(from:Nios II Classic Processor Reference Guide)

1、Register File

The Nios II architecture supports a flat register file, consisting of thirty-two 32-bit general-purpose integer registers, and up to thirty-two 32-bit control registers.

The architecture supports supervisor and user modes that allow system code to protect the control registers from errant applications.

The Nios II processor can optionally have one or more shadow register sets. A shadow register set is a complete set of Nios II general-purpose registers. When shadow register sets are implemented, the CRS field of the status register indicates which register set is currently in use. An instruction access to a general-purpose register uses whichever register set is active.
A typical use of shadow register sets is to accelerate context switching. When shadow register sets are implemented, the Nios II processor has two special instructions, rdprs and wrprs, for moving data between register sets. Shadow register sets are typically manipulated by an operating system kernel, and are transparent to application code. A Nios II processor can have up to 63 shadow register sets.

The Nios II architecture allows for the future addition of floating-point registers. For details about shadow register set implementation and usage, refer to “Registers” and “Exception
Processing” in the Programming Model chapter of the Nios II Processor Reference Handbook. For details about the rdprs and wrprs instructions, refer to the Instruction Set Reference chapter of the Nios II Processor Reference Handbook.


2、Arithmetic Logic Unit
 The Nios II ALU operates on data stored in general-purpose registers. ALU operations take one or two inputs from registers, and store a result back in a register. The ALU supports the data operations described in the table below. To implement any other operation, software computes the result by performing a combination of the fundamental operations.


　

3、Custom Instructions
 from:Nios II Custom Instruction user guide.pdf

Nios II custom instructions are custom logic blocks adjacent to the ALU in the processor’s datapath. Custom instructions give you the ability to tailor the Nios II processor core to meet the needs of a particular application. You can accelerate time critical software algorithms by converting them to custom hardware logic blocks. Because it is easy to alter the design of the FPGA-based Nios II processor, custom instructions provide an easy way to experiment with hardware-software tradeoffs at any point in the design process.



Reset and Debug Signals
The table below describes the reset and debug signals that the Nios II processor core supports.

4、5、Exception and Interrupt Controllers
The Nios II processor includes hardware for handling exceptions, including hardware interrupts. It also
includes an optional external interrupt controller (EIC) interface. The EIC interface enables you to speed
up interrupt handling in a complex system by adding a custom interrupt controller.
　

6、7、instruction and data bus

from:Nios II Gen2 Processor Reference Guide

The Nios II architecture supports separate instruction and data buses, classifying it as a Harvard architecture. Both the instruction and data buses are implemented as Avalon-MM master ports that adhere to the Avalon-MM interface specification. The data master port connects to both memory and peripheral components, while the instruction master port connects only to memory components.

Note:

The Nios II instruction and data masters have a combined address map. The memory model is arranged so that instructions and data are in the same address space.
  • Memory and Peripheral Access
    The Nios II architecture provides memory-mapped I/O access. Both data memory and peripherals are mapped into the address space of the data master port. The Nios II architecture uses little-endian byte ordering. Words and halfwords are stored in memory with the more-significant bytes at higher addresses.
  • Instruction Master Port
    The Nios II instruction bus is implemented as a 32-bit Avalon-MM master port. The instruction master port performs a single function: it fetches instructions to be executed by the processor. The instruction master port does not perform any write operations.
  • Data Master Port
    The Nios II data bus is implemented as a 32-bit Avalon-MM master port. The data master port performs two functions:
  • Shared Memory for Instructions and Data
    Usually the instruction and data master ports share a single memory that contains both instructions and data. While the processor core has separate instruction and data buses, the overall Nios II processor system might present a single, shared instruction/data bus to the outside world. The outside view of the Nios II processor system depends on the memory and peripherals in the system and the structure of the system interconnect fabric.


 8、Memory Management Unit

The Nios II processor provides an MMU to support full-featured operating systems. Operating systems that require virtual memory rely on an MMU to manage the virtual memory. When present, the MMU manages memory accesses including translation of virtual addresses to physical addresses, memory protection, cache control, and software process memory allocation.
  • Recommended Usage
    Including the Nios II MMU in your Nios II hardware system is optional. The MMU is only useful with an operating system that takes advantage of it.
  • Memory Management
    Memory management comprises two key functions:
  • Address Space and Memory Partitions
    The MMU provides a 4-GB virtual address space, and is capable of addressing up to 4 GB of physical memory.
  • TLB Organization
    A TLB functions as a cache for the operating system’s page table. In Nios II processors with an MMU, one main TLB is shared by instruction and data accesses. The TLB is stored in on-chip RAM and handles translations for instruction fetches and instructions that perform data accesses.
  • TLB Lookups
    A TLB lookup attempts to convert a virtual address (VADDR) to a physical address (PADDR).

9、Memory Protection Unit

The Nios II processor provides an MPU for operating systems and runtime environments that desire memory protection but do not require virtual memory management. For information about memory protection with virtual memory management, refer to the Memory Management Unit section.

When present and enabled, the MPU monitors all Nios II instruction fetches and data memory accesses to protect against errant software execution. The MPU is a hardware facility that system software uses to define memory regions and their associated access permissions. The MPU triggers an exception if software attempts to access a memory region in violation of its permissions, allowing you to intervene and handle the exception as appropriate. The precise exception effectively prevents the illegal access to memory.

The MPU extends the Nios II processor to support user mode and supervisor mode. Typically, system software runs in supervisor mode and end-user applications run in user mode, although all software can run in supervisor mode if desired. System software defines which MPU regions belong to supervisor mode and which belong to user mode.

  • Memory Regions
    The MPU contains up to 32 instruction regions and 32 data regions. Each region is defined by the following attributes:
  • Overlapping Regions
    The memory addresses of regions can overlap. Overlapping regions have several uses including placing markers or small holes inside of a larger region. For example, the stack and heap may be located in the same region, growing from opposite ends of the address range. To detect stack/heap overflows, you can define a small region between the stack and heap with no access permissions and assign it a higher priority than the larger region. Any access attempts to the hole region trigger an exception informing system software about the stack/heap overflow.
  • Enabling the MPU
    The MPU is disabled on system reset. System software enables and disables the MPU by writing to a control register. Before enabling the MPU, you must create at least one instruction and one data region, otherwise unexpected results can occur. Refer to the Working with the MPU section for more information.


 11、Tightly-Coupled Memory

from：Nios II Classic Processor Reference Guide

The Nios II/f core provides optional tightly-coupled memory interfaces for both instructions and data.

A Nios II/f core can use up to four each of instruction and data tightly-coupled memories. When a tightly-coupled memory interface is enabled, the Nios II core includes an additional memory interface master port. Each tightly-coupled memory interface must connect directly to exactly one memory slave port.

When tightly-coupled memory is present, the Nios II core decodes addresses internally to determine if requested instructions or data reside in tightly-coupled memory. If the address resides in tightly-coupled memory, the Nios II core fetches the instruction or data through the tightly-coupled memory interface. Software accesses tightly-coupled memory with the usual load and store instructions, such as ldw or ldwio.

Accessing tightly-coupled memory bypasses cache memory. The processor core functions as if cache were not present for the address span of the tightly-coupled memory. Instructions for managing cache, such as initd and flushd, do not affect the tightly-coupled memory, even if the instruction specifies an address in tightly-coupled memory.

When the MMU is present, tightly-coupled memories are always mapped into the kernel partition and can only be accessed in supervisor mode.


12、JTAG Debug Module
The Nios II architecture supports a JTAG debug module that provides on-chip emulation features to
control the processor remotely from a host PC. PC-based software debugging tools communicate with the
JTAG debug module and provide facilities, such as the following features:
• Downloading programs to memory
• Starting and stopping execution
• Setting breakpoints and watchpoints
• Analyzing registers and memory
• Collecting real-time execution trace data